`include "defines.v"

module if_id(
input  wire               clock,
	input  wire               reset,
	input  wire[`AddressBus]  if_pc,
	input  wire[`DataBus]     if_instruction,
	input  wire[`STALL_BUS]   stall,
	output reg[`AddressBus]   id_pc,
	output reg[`DataBus]      id_instruction
);

always @ (posedge clock) begin
		if (reset == `ResetEnable) begin
			id_pc <= `ZeroWord;
			id_instruction <= `ZeroWord;
		end else if ((stall[1] == 1'b1) && (stall[2] == 1'b0)) begin
			id_pc <= `ZeroWord;
			id_instruction <= `ZeroWord;
		end else if (stall[1] == 1'b0) begin
			id_pc <= if_pc;
			id_instruction <= if_instruction;
		end
	end

endmodule